The application claims the priority benefit of Taiwan application serial no. 91136630, filed Dec. 19, 2002.
1. Field of Invention
The present invention generally relates to a clock generating circuit, and more particularly, to a clock generating circuit in which the frequency of the output clock can be arbitrarily changed and a method thereof.
2. Description of Related Art
Besides the system clock provided by the system itself, other clocks with frequency different from the system clock are also frequently used in the electronic circuit system. When the required frequency of the clock is an integer times of the frequency of the system clock, the function can be solely achieved by the divider. However, it is common that the required frequency of the clock is not right at an integer times of the frequency of the system clock, e.g. the 115.2 KHz used by the serial port and the 44.1 KHz used by the audio encoding and decoding. In such a case, the 2n divider can not achieve the required function.
Therefore, the only way to implement it is using the method of the phase lock loop (PLL) or the state machine. However, the frequency ratio between the required clock and the system clock generated by the method of either PLL or the state machine is fixed after the design is completed. When the frequency of the system clock or the required clock is changed, the circuit is required to be redesigned and time and cost waste occur.
To solve the problem mentioned above, a clock generating circuit and a method thereof are provided by the present invention. It is not required to redesign the circuit when the frequency of the system clock or the required clock is changed, so that the frequency of the output clock generated can be arbitrarily changed according to the frequency ratio between the system clock and the required output clock.
In order to achieve the object mentioned above and others, the present invention provides a clock generating circuit. The clock generating circuit is suitable for generating a first output clock from a system clock, wherein the frequency ratio between the first output clock and the system clock is a value of the first preset value divided by the second preset value. The clock generating circuit comprises a register, a first adder, a first comparator, a second adder, and a multiplexer.
The register temporality stores a data value according to a trigger from the system clock. The first adder coupled to the register is used to receive the data value mentioned above and obtain a sum of the data value and the first preset value so as to output a first result. The first comparator coupled to the first adder is used to compare the first result with a reference value so as to generate a required first output clock. The second adder coupled to the first adder is used to receive the first result and obtain a sum of the first result and the second preset value so as to output a second result. The multiplexer couples to the first adder, the second adder, the first comparator, and the register. The multiplexer is used to select the data value that should be stored into the register at next system clock from the first result and the second result according to the level of the first output clock.
In an embodiment of the present invention, the magnitude of the first preset value and the second preset value is a value of the frequency of the first output clock and the frequency of the system clock divided by a GCF (Greatest Common Factor) of the frequency of the first output clock and the frequency of the system clock, respectively, so that the circuit design can be simplified.
In an embodiment of the present invention, a positive first preset value is input into the first adder, and a negative second preset value is input into the second adder. When the system is reset, the initial data value is set to 0, and the reference value is set to equal the second preset value. Each time when the first result is not smaller than the reference value, the first comparator generates a pulse of the first output clock. Moreover, each time when the pulsed is generated, the multiplexer selects the second result as the data value that should be stored into the register at next system clock.
In the other embodiment of the present invention, a negative first preset value is input into the first adder, and a positive second preset value is input into the second adder. When the system is reset, the initial data value is set to equal the second preset value, and the reference value is set to 0. Each time when the first result is not greater than 0, the first comparator generates a pulse of the first output clock. Moreover, each time when the pulse is generated, the multiplexer selects the second result as the data value that should be stored into the register at next system clock.
In either embodiment of the present invention, the clock generating circuit further comprises a second comparator. The second comparator coupled to the register is used to compare the data value with a third preset value that is smaller than the second preset value, so as to generate a second output clock. Preferably, the third preset value is a rounded integer of a half of the second preset value, so as to adjust the duty of the output clock.
The present invention further provides a clock generating method. The clock generating method is suitable for generating a first output clock from a system clock. Wherein, the frequency ratio between the first output clock and the system clock is a value of the first preset value divided by the second preset value. The clock generating method comprises the steps of: first, obtaining a sum of a data value and the first preset value so as to generate a first result; obtaining a sum of the first result and the second preset value so as to generate a second result; selecting a data value that should be stored into the register at next system clock from the first result and the second result according to the level of the first output clock; and comparing the first result with a reference value so as to generate a first output clock.
Preferably, the magnitude of the first preset value and the second preset value is a value of the frequency of the first output clock and the frequency of the system clock divided by a GCF of the frequency of the first output clock and the frequency of the system clock, respectively.
Wherein, when obtaining the first result and the second result, a positive first preset value and a negative second preset value are used to obtain the summation. Moreover, the initial data value is set to 0, and the reference value is set to equal the second preset value. Each time when the first result is not smaller than the reference value, a pulse of the first output clock is generated. Furthermore, each time when the pulsed is generated, the second result is selected as the data value that should be stored into the register at next system clock.
Wherein, when obtaining the first result and the second result, a negative first preset value and a positive second preset value are used to obtain the summation. Moreover, the initial data value is set to the second preset value, and the reference value is set to 0. Each time when the first result is not greater than 0, a pulse of the first output clock is generated. Furthermore, each time when the pulse is generated, the second result is selected as the data value that should be stored into the register at next system clock.
A step of comparing the data value with a third preset value that is smaller than the second preset value so as to generate a second output clock is further comprised. Preferably, the third preset value is a rounded integer of a half of the second preset value.
From descriptions mentioned above, with the clock generating circuit and the method thereof of the present invention, the frequency of the output clock generated can be arbitrarily changed according to the frequency ratio between the system clock and the required clock when the frequency of the system clock or the required clock is changed. Therefore, It is not required to redesign the circuit and the time and cost waste can be eliminated.